> The two L1 carrier components modulated by the two separate bit trains (C/A-code plus data and P(Y)-code
> plus data) shall be in phase quadrature (within ±100 milliradians) with the C/A signal carrier lagging the P
> signal by 90 degrees
Another confusing thing is the GPS doc says In phase is P(Y) xor D(t) while Quadrature is C/A xor D(t), but the MAX2769 seems to operate where I is the C/A code since that's the only component the STM32 based GPS receiver uses. However, the diagram in the MAX2769 seems to have Q be +90deg phase shift ahead of I, whereas in the GPS document C/A lags by 90deg behind P(y) so I in GPS doc is +90deg phase shift ahead of Q in gps doc, so i guess the receiver and the doc have opposite conventions?
https://www.xilinx.com/support/answers/65240.html https://old.reddit.com/r/FPGA/comments/e5e8ia/be_aware_of_zynq_7020_arm_core_1_bricking_due_to/ Seems important for devboard