Wrap up study notes for this sem

_posts/2024-08-19-ELEC4406ELEC2311-notes-and-tips.md

@@ -8,9 +8,9 @@ toc: true
 # image: assets/img/2024-08-19-ELEC4406ELEC2311-not/preview.png
 ---
 
-# Notes for ELEC4406
+Some useful notes/code for the class tests 1 and 2, the lab test and exam.
 
-## lab-test tips
+## Lab test tips
 
 The lab test has a very high time pressure (kind of like comms if you have/are doing it).
 
@@ -27,7 +27,7 @@ The lab test has a very high time pressure (kind of like comms if you have/are d
 - **NOTE: Check for your current year**. As of 2024, you may use your personal computer in the test and you don't need to use the lab computers (subject to same restrictions). You may not use anything other than Altera Quartus, Modelsim and Adobe Acrobat. You _cannot_ use vscode.
 - Make a few project files and the directory structure before the test, DO NOT put modelsim project in the same directory as code.
 
-```
+```text
 [SID]
   -> SYNTH
     -> Part1
@@ -260,6 +260,8 @@ Look at Expr evaluation value to decide if change should be rejected (not inputs
 
 Make table like this for delta time (required for followthrough marks):
 
+NOTE: In 2024's papers, this table template was already included in the question sheet so you don't need to memorise the columns.
+
 | Time  | Event | Processes triggered | Transactions enqueued | Causes event? |
 | ----- | ----- | ------------------- | --------------------- | ------------- |
 | 5 ns  | E->1  | U1                  | 10ns:E->0             | Y             |
@@ -275,13 +277,13 @@ Make table like this for delta time (required for followthrough marks):
 
 ## Test 2
 
-### TEST 2 CAN HAVE ANY CONTENT FROM TEST 1!
+### TEST 2 CAN HAVE ANY CONTENT FROM TEST 1
 
 Do not forget how to do delta delay, timing diagrams, VHDL -> diagram or diagram -> VHDL.
 
 ### Test vectors ⚠
 
-**Can be expressed using X for don't care**, do not need to enumerate every combination.
+**Can be expressed using X for don't care** in tests/exams, do not need to enumerate every combination.
 
 Example: "`11X0X`"
 
@@ -295,6 +297,10 @@ Re-remember these identities again for XOR method
 | De Morgan's law | $\overline{AB}=\overline A+\overline B$ | $\overline{A+B}=\overline A\cdot\overline B$ |
 | Idempotency     | $AA=A$                                  | $A+A=A$                                      |
 
+### Path sensitization
+
+Make sure to do the workshop question which has a branch after the fault! Understand how to identify the three paths (two single and one multiple).
+
 ## Timing
 
 $$
@@ -305,6 +311,33 @@ $$
 \end{align*}
 $$
 
+## Exam study
+
+### Extra papers
+
+Past exam papers are not provided, but from my 2024 experience the workshops and past tests are more than adequate for the exam questions.
+
+If you need more questions, search "**ENGT2301**" on OneSearch. You will find a 2005 paper (note the 2005 deferred has the same questions). There's some obsolete questions involving JK flip-flops, but there's some useful ones on timing, state machines and path sensitization.
+
+### **2024 EXAM OUTLINE IMPORTANT**
+
+This was quoted from the final lecture.
+
+- 5 questions x 20 marks
+- **1** Testing 25 marks
+  - No _XOR method_ (XOR can be used still for validation)
+  - Path sensitization
+- **2** Read VHDL (???)
+- **3** VHDL -> Draw circuit
+- **4** Circuit -> VHDL
+- **5** Timing question (practical 5)
+- 10 marks allocated to general questions
+- NOTE: In the 2024 examination, calculators were allowed which was useful for the timing questions.
+
+### Implementation technologies
+
+- No practice questions, but may have worded questions
+
 ## Issues with saving file/modifying files not updating the simulation
 
 The optimizer is once again causing issues.
@@ -353,51 +386,6 @@ Alternatively, add `+acc` to `voptargs` if you are using the TCL command line:
 vsim $TESTBENCH_ID -voptargs=+acc; add wave *
 ```
 
-## Dark mode in intel quartus
+## Dark mode in Intel/Altera Quartus
 
-Run this script I made on windows. [🔗Link](https://github.com/peter-tanner/Intel-Quartus-Dark-Mode-Windows)
-
-## Exam study
-
-### **2024 EXAM OUTLINE IMPORTANT**
-- 5 questions x 20 marks
-- **1** Testing 25 marks
-  - No _XOR method_ (XOR can be used still for validation)
-  - Path sensitization
-- **2** Read VHDL (??? so probably a delta time question)
-- **3** VHDL -> Draw circuit
-- **4** Circuit -> VHDL
-- **5** Timing question (practical 5)
-- 10 marks allocated to general questions
-
-### Implementation technologies
-
-- No practice questions, but may have worded questions
-
-Partitioning
-
-
->    Yeah, you can implement, you know, in any any function,
->    uh, partition is important to understand why we do partitioning.
->    I'm not gonna ask you this, OK, because, uh, you
->    know, some of you may have forgotten this.
->    Uh, we're going at a bit a bit higher level,
->    Uh, but it's good to to to to know what
->    is behind, uh, below the the surface.
-
->    Uh uh, So there won't be any problems per SE.
->   It's more, uh, an overview of of of the FPG.
->   Uh, so I want to ask you to implement, but
->   I may ask you questions.
->   You know why, uh, why do we you know, why
->   would we need a large look up table or whatever?
->   Any questions?
->   All right.
-
-
-PAL > CPLD > FPGA > standard cell > custom design
-
-### LECTURES TO WATCH
-
-- [(low-med priority, has a video which might be asked in final) Digital System Design - ELEC2311_SEM-2_2024 / ELEC2311 - 17 Sep 2024, 10:00 - Lecture - Tue 17, Sept](https://echo360.net.au/lesson/G_d242de04-466c-4e5c-90c5-8559bf05817a_f680b162-bea0-4466-ba23-9c4e4e8608f4_2024-09-17T09:58:00.000_2024-09-17T11:52:00.000/classroom)
-- [(low priority, already tested to success) Digital System Design - ELEC2311_SEM-2_2024 / ELEC2311 - 18 Sep 2024, 09:00 - Lecture - Wed 18, Sept](https://echo360.net.au/lesson/G_cd2b8e85-7208-4aef-bd38-9ec27622ec31_f680b162-bea0-4466-ba23-9c4e4e8608f4_2024-09-18T08:58:00.000_2024-09-18T09:52:00.000/classroom)
+Run this script I made on Windows. [🔗Link](https://github.com/peter-tanner/Intel-Quartus-Dark-Mode-Windows)

_posts/2024-10-29-Idiots-guide-to-ELEC4402-Communications-Systems.md

@@ -52,6 +52,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
   - ENGT4301 Digital Communications and Networking
   - ELEC3302 Communications Systems
   - Note that ELEC5501 Advanced Communications is a different unit.
+- To be honest, you select (relevant) questions from these for class test study as well.
 
 <details>
 <summary>Listing of examination papers on OneSearch</summary>
@@ -71,6 +72,16 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
 - This formula sheet will attempt to condense all processes/formulas you may need in this unit.
 - **You do not get given a formula sheet**, so you are entirely dependent on your own notes (except for some exceptions, such as the $\text{erf}(x)$ table). So bring good notes.
 - Doing this unit after signal processing is a good idea.
+- Try to practice questions from the exam papers on OneSearch mentioned above before class test, since you don't get past questions for the tests.
+
+### Final exam 2024
+
+As quoted from the lectures:
+
+- No short questions
+- 10 calculation questions
+- From exam front page: Any printed or written material (e.g. dictionaries, textbooks, statutes, cases, legislation, annotations, lecture notes, tutorials with solutions, notes) except UWA Library books. Photocopied or printed eBook of a textbook is permitted.
+  - So yes you can still bring as many papers as you want to the final, unlike in signals and systems/signal processing where the final only allowed two pages.
 
 ## Printable notes begins on next page (in PDF)