mirror of
https://github.com/peter-tanner/satellite-testing-system.git
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897 lines
47 KiB
C
897 lines
47 KiB
C
/**
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******************************************************************************
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* @file stm32l4xx_hal_mmc.h
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* @author MCD Application Team
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* @brief Header file of MMC HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32L4xx_HAL_MMC_H
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#define STM32L4xx_HAL_MMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l4xx_hal_def.h"
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#include "stm32l4xx_ll_sdmmc.h"
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/** @addtogroup STM32L4xx_HAL_Driver
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* @{
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*/
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#if defined(SDMMC1)
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/** @addtogroup MMC
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* @brief MMC HAL module driver
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup MMC_Exported_Types MMC Exported Types
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* @{
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*/
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/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
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* @{
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*/
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typedef enum
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{
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HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
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HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
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HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
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HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
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HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
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HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
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HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
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HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
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}HAL_MMC_StateTypeDef;
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
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* @{
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*/
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typedef uint32_t HAL_MMC_CardStateTypeDef;
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#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */
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#define HAL_MMC_CARD_READY 0x00000001U /*!< Card is in ready state (can't be checked by CMD13) */
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#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */
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#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
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#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
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#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
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#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
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#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
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#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
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#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */
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#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */
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#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
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* @{
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*/
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#define MMC_InitTypeDef SDMMC_InitTypeDef
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#define MMC_TypeDef SDMMC_TypeDef
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/**
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* @brief MMC Card Information Structure definition
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*/
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typedef struct
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{
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uint32_t CardType; /*!< Specifies the card Type */
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uint32_t Class; /*!< Specifies the class of the card class */
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uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
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uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
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uint32_t BlockSize; /*!< Specifies one block size in bytes */
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uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
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uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
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}HAL_MMC_CardInfoTypeDef;
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/**
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* @brief MMC handle Structure definition
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*/
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
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typedef struct __MMC_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
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{
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MMC_TypeDef *Instance; /*!< MMC registers base address */
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MMC_InitTypeDef Init; /*!< MMC required parameters */
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HAL_LockTypeDef Lock; /*!< MMC locking object */
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uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
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uint32_t TxXferSize; /*!< MMC Tx Transfer size */
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uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
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uint32_t RxXferSize; /*!< MMC Rx Transfer size */
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__IO uint32_t Context; /*!< MMC transfer context */
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__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
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__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
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#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
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DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
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DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
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#endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
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HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
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uint32_t CSD[4U]; /*!< MMC card specific data table */
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uint32_t CID[4U]; /*!< MMC card identification number table */
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uint32_t Ext_CSD[128];
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
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void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc);
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#endif
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void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
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void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
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#endif
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}MMC_HandleTypeDef;
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
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* @{
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*/
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typedef struct
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{
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__IO uint8_t CSDStruct; /*!< CSD structure */
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__IO uint8_t SysSpecVersion; /*!< System specification version */
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__IO uint8_t Reserved1; /*!< Reserved */
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__IO uint8_t TAAC; /*!< Data read access time 1 */
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__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
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__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
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__IO uint16_t CardComdClasses; /*!< Card command classes */
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__IO uint8_t RdBlockLen; /*!< Max. read data block length */
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__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
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__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
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__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
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__IO uint8_t DSRImpl; /*!< DSR implemented */
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__IO uint8_t Reserved2; /*!< Reserved */
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__IO uint32_t DeviceSize; /*!< Device Size */
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__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
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__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
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__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
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__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
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__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
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__IO uint8_t EraseGrSize; /*!< Erase group size */
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__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
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__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
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__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
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__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
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__IO uint8_t WrSpeedFact; /*!< Write speed factor */
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__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
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__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
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__IO uint8_t Reserved3; /*!< Reserved */
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__IO uint8_t ContentProtectAppli; /*!< Content protection application */
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__IO uint8_t FileFormatGroup; /*!< File format group */
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__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
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__IO uint8_t PermWrProtect; /*!< Permanent write protection */
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__IO uint8_t TempWrProtect; /*!< Temporary write protection */
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__IO uint8_t FileFormat; /*!< File format */
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__IO uint8_t ECC; /*!< ECC code */
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__IO uint8_t CSD_CRC; /*!< CSD CRC */
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__IO uint8_t Reserved4; /*!< Always 1 */
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}HAL_MMC_CardCSDTypeDef;
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
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* @{
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*/
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typedef struct
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{
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__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
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__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
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__IO uint32_t ProdName1; /*!< Product Name part1 */
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__IO uint8_t ProdName2; /*!< Product Name part2 */
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__IO uint8_t ProdRev; /*!< Product Revision */
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__IO uint32_t ProdSN; /*!< Product Serial Number */
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__IO uint8_t Reserved1; /*!< Reserved1 */
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__IO uint16_t ManufactDate; /*!< Manufacturing Date */
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__IO uint8_t CID_CRC; /*!< CID CRC */
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__IO uint8_t Reserved2; /*!< Always 1 */
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}HAL_MMC_CardCIDTypeDef;
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/**
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* @}
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*/
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
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/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
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* @{
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*/
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typedef enum
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{
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HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
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HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
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HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
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HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
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#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */
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HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */
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HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */
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HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */
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#endif
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HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
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HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
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}HAL_MMC_CallbackIDTypeDef;
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
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* @{
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*/
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typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
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/**
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* @}
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*/
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#endif
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup MMC_Exported_Constants Exported Constants
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* @{
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*/
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#define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
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/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
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* @{
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*/
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#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
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#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
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#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
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#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
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#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
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#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
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#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
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#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
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#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
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number of transferred bytes does not match the block length */
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#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
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#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
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#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
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#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
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command or if there was an attempt to access a locked card */
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#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
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#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
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#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
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#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
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#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
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#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
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#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
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#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
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#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
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#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
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#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
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of erase sequence command was received */
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#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
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#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
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#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
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#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
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#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
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#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
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#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
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#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
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#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
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#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
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#endif
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
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* @{
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*/
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#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
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#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
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#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
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#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
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#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
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#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
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#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
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* @{
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*/
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/**
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* @brief
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*/
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#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
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#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
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#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
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#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
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#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
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#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
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#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
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* @{
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*/
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#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */
|
|
#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
|
/** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type
|
|
* @{
|
|
*/
|
|
#define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */
|
|
#define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */
|
|
#define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */
|
|
#define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */
|
|
#define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */
|
|
#define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */
|
|
|
|
#define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \
|
|
((TYPE) == HAL_MMC_TRIM) || \
|
|
((TYPE) == HAL_MMC_DISCARD) || \
|
|
((TYPE) == HAL_MMC_SECURE_ERASE) || \
|
|
((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \
|
|
((TYPE) == HAL_MMC_SECURE_TRIM_STEP2))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type
|
|
* @{
|
|
*/
|
|
#define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */
|
|
#define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */
|
|
#define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */
|
|
#define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */
|
|
|
|
|
|
#define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \
|
|
((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \
|
|
((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \
|
|
((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED))
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macro ------------------------------------------------------------*/
|
|
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
|
* @brief macros to handle interrupts and specific clock configurations
|
|
* @{
|
|
*/
|
|
/** @brief Reset MMC handle state.
|
|
* @param __HANDLE__ : MMC handle.
|
|
* @retval None
|
|
*/
|
|
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
|
|
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
|
(__HANDLE__)->State = HAL_MMC_STATE_RESET; \
|
|
(__HANDLE__)->MspInitCallback = NULL; \
|
|
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
} while(0)
|
|
#else
|
|
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
|
|
#endif
|
|
|
|
#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
|
|
/**
|
|
* @brief Enable the MMC device.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
|
|
|
/**
|
|
* @brief Disable the MMC device.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
|
|
|
/**
|
|
* @brief Enable the SDMMC DMA transfer.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
|
|
|
/**
|
|
* @brief Disable the SDMMC DMA transfer.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Enable the MMC device interrupt.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
|
|
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
|
|
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
|
|
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
|
|
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Disable the MMC device interrupt.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
|
|
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
|
|
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
|
|
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
|
|
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Check whether the specified MMC flag is set or not.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __FLAG__ specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
|
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
|
|
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
|
|
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
|
|
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
|
|
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
|
|
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
|
|
* @arg SDMMC_FLAG_RXACT: Data receive in progress
|
|
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
|
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
|
|
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
|
|
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
|
|
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
|
|
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
|
|
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
|
|
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
|
|
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
|
|
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
|
|
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
|
|
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
|
|
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
|
|
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
|
|
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
|
|
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
|
|
* @retval The new state of MMC FLAG (SET or RESET).
|
|
*/
|
|
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
|
|
|
/**
|
|
* @brief Clear the MMC's pending flags.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __FLAG__ specifies the flag to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
|
|
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
|
|
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
|
|
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
|
|
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
|
|
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
|
|
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
|
|
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
|
|
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
|
|
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
|
|
|
/**
|
|
* @brief Check whether the specified MMC interrupt has occurred or not.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
|
|
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
|
|
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
|
|
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
|
|
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
|
|
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
|
|
* @retval The new state of MMC IT (SET or RESET).
|
|
*/
|
|
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Clear the MMC's interrupt pending bits.
|
|
* @param __HANDLE__ MMC Handle
|
|
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
|
|
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
|
|
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
|
|
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
|
|
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
|
|
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
|
|
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
|
|
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
|
|
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
|
/* Include MMC HAL Extension module */
|
|
#include "stm32l4xx_hal_mmc_ex.h"
|
|
#endif
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup MMC_Exported_Functions
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup MMC_Exported_Functions_Group1
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
|
|
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
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HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
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void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
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void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
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/**
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* @}
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*/
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/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
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* @{
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*/
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/* Blocking mode: Polling */
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HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
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HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
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HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
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/* Non-Blocking mode: IT */
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HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
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HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
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/* Non-Blocking mode: DMA */
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HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
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HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
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|
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void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
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/* Callback in non blocking modes (DMA) */
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void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
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void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
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void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
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void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
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#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
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/* MMC callback registering/unregistering */
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HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
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HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
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#endif
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/**
|
|
* @}
|
|
*/
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|
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/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
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* @{
|
|
*/
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HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
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|
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
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|
#endif
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/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
|
* @{
|
|
*/
|
|
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
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|
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
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|
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
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|
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
|
|
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
|
* @{
|
|
*/
|
|
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
|
|
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
|
|
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
|
|
/**
|
|
* @}
|
|
*/
|
|
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
|
/** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
|
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc);
|
|
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode);
|
|
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
|
|
HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private types -------------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Types MMC Private Types
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private defines -----------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Defines MMC Private Defines
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private variables ---------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Variables MMC Private Variables
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private constants ---------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Constants MMC Private Constants
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private macros ------------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Macros MMC Private Macros
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private functions prototypes ----------------------------------------------*/
|
|
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
/** @defgroup MMC_Private_Functions MMC Private Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
|
|
#endif /* STM32L4xx_HAL_MMC_H */
|