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247 lines
17 KiB
Markdown
247 lines
17 KiB
Markdown
---
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title: ELEC4406/ELEC2311 notes and tips
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author: peter
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date: 2024-08-19 02:26:49 +0800
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categories: [Blogging] # Blogging | Electronics | Programming | Mechanical | SelfHosting
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tags: [getting started] # systems | embedded | rf | microwave | electronics | solidworks | automation | tip
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# image: assets/img/2024-08-19-ELEC4406ELEC2311-not/preview.png
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---
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## Issues with saving file/modifying files not updating the simulation
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The optimizer is once again causing issues.
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My recommendation is to use `qrun` and do things in the terminal with `assert`s instead of trying to do it graphically using the verification diagrams. It also is much quicker.
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For some reason, I can't get incremental compilation working and it just causes more issuse than the time it saves right now, since it results in changes not affecting the simulation, so for now I am cleanly rebuilding each simulation.
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In GUI mode, manually start the simulation. When you need to update the simulation run this commandline
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<!--
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```bash
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qrun $FILE_NAME -optimize -cleanlib -top $TOP_LEVEL_ENTITY; restart -force; run -all
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``` -->
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```bash
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vcom *.vhd; restart -force; run -all
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```
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Here's also how to run the simulation in headless mode from a commandline (Do not run from Questa GUI, since it will make Questa quit)
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```bash
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qrun $FILE_NAME -optimize -simulate -cleanlib -top $TOP_LEVEL_ENTITY
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```
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## No objects appearing in modelsim/questa for testbenches
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⚠ TODO: Fix previous issue in GUI as well (I am now using qrun instead of the GUI).
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This is because the signals are being optimized out since they aren't really used for anything useful.
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The intel questa/modelsim version shipped with the unit is 18.1, but this allowed vopt to be disabled. This is no longer the case on the latest versions of intel questa (You will get a compile error if you disable vopt flow).
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Go to `Simulate > Start Simulation...`, ensure optimization is enabled then click on `Optimization Options...`
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Then select `Apply full visibility to all modules(full debug mode)` and press `OK`.
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## Dark mode in intel quartus
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Run this script I made on windows. [🔗Link](https://github.com/peter-tanner/Intel-Quartus-Dark-Mode-Windows)
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## Test 1
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### Types
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- structual modelling => describe connections between entities using `port map`
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- dataflow modelling => concurrent execution of statements
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```vhdl
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A<=B;
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C<=A;
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...
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```
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- behavioral modelling => sequential execution
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###
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- Signals - signals are only mutated when the process finishes.
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- Variables - variables are mutated at each statement in the process.
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### Evaluation of process manually
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- Double-check at end of first execution the sensitivity list to see if anything changes again
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### Delay
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Look at Expr evaluation value to decide if change should be rejected (not inputs)
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- Transport `O <= TRANSPORT Expr AFTER 10 ns;`
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- Inertial `O <= REJECT 10 ns INERTIAL Expr AFTER 10 ns;`
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- Inertial `O <= Expr AFTER 10 ns;` (Inertial delay: `10 ns`, same as transport component)
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- Delta time `O <= Expr` (Implicit - delta time is applied to concurrent statements when a statement is dependent on the output of a previous one. Expressions which can be executed concurrently have the same delta time)
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Make table like this for delta time (required for followthrough marks):
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| Time | Event | Processes triggered | Transactions enqueued | Causes event? |
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| ----- | ----- | ------------------- | --------------------- | ------------- |
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| 5 ns | E->1 | U1 | 10ns:E->0 | Y |
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| 10 ns | E->0 | U1 | 15ns:E->1 | Y |
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| ... | ... | ... | ... | ... |
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### CHECKLIST
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- Check for statements where inputs are assigned to or outputs are read from
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- Use signals instead
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- Do not include data in sensitivity list for flip flops.
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- Process: only use tokens with `sequential-statement` (`when` is not sequential)
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## Lab quick reference
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Tip: when using pin planner, you can copy paste multiple selections if you are using vscode multi cursors and copying from the markdown version of this page. Useful for filling out seven segment displays.
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| Key | Value | Notes |
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| ----------------------------- | -------------- | -------------------------------------------------------------------------------------- |
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| Part number | 10M50DAF484C7G | |
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| 50 MHz signal (MAX10_CLK1_50) | PIN_P11 | |
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| KEY0 | PIN_B8 | Default: HIGH (Pullup). ⚠ IMPORTANT: USE 2.5V Schmitt trigger I/O standard to debounce |
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| KEY1 | PIN_A7 | Default: HIGH (Pullup). ⚠ IMPORTANT: USE 2.5V Schmitt trigger I/O standard to debounce |
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| SW0 | PIN_C10 | |
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| SW1 | PIN_C11 | |
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| SW2 | PIN_D12 | |
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| SW3 | PIN_C12 | |
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| SW4 | PIN_A12 | |
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| SW5 | PIN_B12 | |
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| SW6 | PIN_A13 | |
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| SW7 | PIN_A14 | |
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| SW8 | PIN_B14 | |
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| SW9 | PIN_F15 | |
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| LEDR0 | PIN_A8 | |
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| LEDR1 | PIN_A9 | |
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| LEDR2 | PIN_A10 | |
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| LEDR3 | PIN_B10 | |
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| LEDR4 | PIN_D13 | |
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| LEDR5 | PIN_C13 | |
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| LEDR6 | PIN_E14 | |
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| LEDR7 | PIN_D14 | |
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| LEDR8 | PIN_A11 | |
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| LEDR9 | PIN_B11 | |
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| HEX00 | PIN_C14 | |
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| HEX01 | PIN_E15 | |
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| HEX02 | PIN_C15 | |
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| HEX03 | PIN_C16 | |
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| HEX04 | PIN_E16 | |
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| HEX05 | PIN_D17 | |
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| HEX06 | PIN_C17 | |
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| HEX07 | PIN_D15 | DECIMAL POINT |
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| HEX10 | PIN_C18 | |
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| HEX11 | PIN_D18 | |
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| HEX12 | PIN_E18 | |
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| HEX13 | PIN_B16 | |
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| HEX14 | PIN_A17 | |
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| HEX15 | PIN_A18 | |
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| HEX16 | PIN_B17 | |
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| HEX17 | PIN_A16 | DECIMAL POINT |
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| HEX20 | PIN_B20 | |
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| HEX21 | PIN_A20 | |
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| HEX22 | PIN_B19 | |
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| HEX23 | PIN_A21 | |
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| HEX24 | PIN_B21 | |
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| HEX25 | PIN_C22 | |
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| HEX26 | PIN_B22 | |
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| HEX27 | PIN_A19 | DECIMAL POINT |
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| HEX30 | PIN_F21 | |
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| HEX31 | PIN_E22 | |
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| HEX32 | PIN_E21 | |
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| HEX33 | PIN_C19 | |
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| HEX34 | PIN_C20 | |
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| HEX35 | PIN_D19 | |
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| HEX36 | PIN_E17 | |
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| HEX37 | PIN_D22 | DECIMAL POINT |
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| HEX40 | PIN_F18 | |
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| HEX41 | PIN_E20 | |
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| HEX42 | PIN_E19 | |
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| HEX43 | PIN_J18 | |
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| HEX44 | PIN_H19 | |
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| HEX45 | PIN_F19 | |
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| HEX46 | PIN_F20 | |
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| HEX47 | PIN_F17 | DECIMAL POINT |
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| HEX50 | PIN_J20 | |
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| HEX51 | PIN_K20 | |
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| HEX52 | PIN_L18 | |
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| HEX53 | PIN_N18 | |
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| HEX54 | PIN_M20 | |
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| HEX55 | PIN_N19 | |
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| HEX56 | PIN_N20 | |
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| HEX57 | PIN_L19 | DECIMAL POINT |
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identity:
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```vhdl
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"000000001"
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"000000010"
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"000000100"
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"000001000"
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"000010000"
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"000100000"
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"001000000"
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"010000000"
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"100000000"
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```
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## identities
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| Name | 1 | 2 |
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| --------------- | --------------------------------------- | -------------------------------------------- |
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| Absorption rule | $A(A+B)=A$ | $A+AB=A$ |
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| De Morgan's law | $\overline{AB}=\overline A+\overline B$ | $\overline{A+B}=\overline A\cdot\overline B$ |
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| Idempotency | $AA=A$ | $A+A=A$ |
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## fsm template
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```vhdl
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entity fsm is port (
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clk,nrst,x in : std_logic;
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...
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);
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end fsm;
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architecture behavioral of fsm is
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type state is {sdefault, s1, s2, ...};
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signal ps, ns : state; -- present_state, next_state
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begin
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process (clk, nrst)
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begin
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if (nrst = '0') then
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ps <= sdefault;
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elsif (rising_edge(clk)) then
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ps <= ns;
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end if;
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end process;
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process (x,ps)
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begin
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case x is
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when s1 =>
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[...]
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end process;
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end behavioral;
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```
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## lab-test tips
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The lab test has a very high time pressure (kind of like comms if you have/are doing it).
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- Use the DE-10 board project template to prevent wasting time entering pin definitions in the pin planner GUI.
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- Bring in components for clock divider, 7 segment display, FSM template and all lab materials at the minimum.
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- Focus on getting a working design before moving on to another design, they will only give one mark if your design has code, but you can't demonstrate it working (mock lab test). If your working design has a bug then they don't take too many marks away in my experience (mock lab test: I had a speed switch erroneously affect both speed and direction of a FSM - this only copped a 1 mark penalty in the mock lab test).
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- Enable autocomplete. It's better than nothing, but it's definitely not intellisense.
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- **Check for your current year**. As of 2024, you may use your personal computer in the test and you don't need to use the lab computers (subject to same restrictions). You may not use anything other than Altera Quartus, Modelsim and Adobe Acrobat. You _cannot_ use vscode.
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